Method and system for controlling and exchanging data for multimedia appliances and an appliance suitable therefor

ABSTRACT

The present invention relates to a method and a system for controlling and/or exchanging data for multimedia appliances and an appliance suitable therefor According to prior art, methods and systems for controlling and exchanging data for multimedial appliances have the disadvantage that said methods, systems and appliances are very simple with regard to the requirements and the possibilities at hand and involve considerable hardware requirements. The invention is based upon the fact that each appliance which is integrated into the system sends a message at regular intervals and by means of the bus as soon as said appliance has been activated The type of the appliance can be detected by means of said message which also reveals that the appliance is switched on, i.e. active. All the remaining active appliances in the system evaluate said messages and send such messages themselves as long as said appliances are active. The active appliances can control other active appliances or exchange data with other active appliances if required because each active appliance is thus provided with information on the other active appliances in the system.

[0001] The present invention is concerned with a method and a system forcontrolling and/or

[0002] exchanging data for multimedia appliances as well as an appliancesuitable for it. Methods and systems for controlling and/or exchangingdata for multimedia appliances, for example, electronics entertainmentappliances, have become known in the past, using a link between theindividual appliances, for example, a bus.

[0003] In the Sat-Link system, a link between a satellite receiver and avideo recorder is utilized. The video recorder controls, in the timermode, that is, when the recording of a broadcast of a certain broadcastchannel is programmed, the tuning circuit of the satellite receiver, inorder to select the corresponding broadcast channel in the satellitereceiver. It is not possible to transfer acknowledgements, rather,unidirectional control commands are transferred from the video recorderto the satellite receiver exclusively. Only the more recent satellitereceiver modules for TV appliances make acknowledgement possible incombination with a corresponding video recorder, through pin 8 of theSCART socket. Here, bidirectional communication is simulated crossconnection of two unidirectional connections. The control commandsreceived by the TV appliance are further conducted through pin 8 of theSCART socket to the connected video recorder and/or satellite receiver.As a result of this, the connected appliance can be operated in spite ofshading of the IR receiver, for example, when a closed rack isincorporated.

[0004] A bus concept for electronics entertainment appliances has becomeknown under the name Megalogic; this is produced and distributed by theApplicant. In this system, communication and turning on of theappliance, for example, TV appliance, video recorder and satellitereceiver becomes possible. The data rate is about 200 bps, and the datasignal is transferred to pin 10 of the SCART socket. The individualconnections are turned on through open collector stages. The networktopology normally consists of linking peer-to-peer connections, but canalso be realized electrically with a SCART distributor. In principle,there are 16 fixed appliance addresses (0-15).

[0005] Other buses for control of data exchange are based, for example,on the standard IEEE1394 and make the so-called “Hot Plug & Play”possible, that is, appliances can be integrated newly into the bus andput into operation immediately without initialization of the newappliance being necessary. Arbitrary turning on and turning off of theappliances is also possible and is recognized in the system, since theindividual appliances have the corresponding hardware prerequisites. Inthese systems, a definition is planned which is universal for themanufacturer, and thus, using digital communication, it is possible tolink various appliances (DVB-STB, Internet-STB, DVD, IDVD, DVCR, GameConsole, TV, and others). Simultaneous transfer of control and AV datais possible.

[0006] The known methods and systems for control and for exchanging ofdata for multimedia appliances, however, all have the disadvantage that,on the one hand, they are very simple—both with regard to the necessaryexpenditure as well as with regard to available possibilities (Sat-Linksystem, Megalogic), where especially the possibility of recognition ofthe turning-on and turning-off processes of the individual appliancesrepresents problems within the system and another disadvantage is thatthey usually require extensive hardware (systems according to IEEE1394).

[0007] Therefore, it is the task of the present invention to give amethod and a system for controlling and/or exchanging of data formultimedia appliances, as well as to provide an appliance suitable forit, which permits an almost arbitrary configuration of the system withlittle additional expenditure and where individual appliances of thesystem can be operated arbitrarily and recognized as well in the systemat all times.

[0008] In the present invention, this task is solved by thecharacteristics of claims 1, 9 and 17

[0009] In the invention, the basic assumption is the consideration thateach of the appliances incorporated into the system sends a messagethrough the bus at regular intervals, as soon as it has becomeactivated. This message allows first of all the recognition of thenature and type of the appliance and, secondly, it can be seen from themessage that the appliance is turned on, that is, it is active. Allother active appliances in the system evaluate these messages andthemselves send such messages as long as they are active. Since, in thisway, each active appliance has information about the other activeappliances in the system, if required, the active appliances can controlother active appliances or exchange data with them.

[0010] The advantage of the device according to the invention should beregarded in the fact that appliances can be linked to each other withalmost no additional circuit-technological expenditure in order tocontrol each other mutually or in order to exchange data with eachother. Appliances which should not be operated at certain times, canalso be separated completely from the energy supply, for example, themain voltage, since they will provide information automatically on theactual status of the other appliances after they had been activated.

[0011] Other advantages of the present invention follow from thedependent Claims, as well as from the description of embodiments of thedevices according to the invention for digital transfer of audio signalsgiven below, with the aid of figures.

[0012] The following are shown:

[0013]FIG. 1 is a schematic representation of a layer model for a systemfor controlling and exchanging of data for multimedia appliances,

[0014]FIG. 2 is a schematic circuit diagram of a system for controllingand exchanging data for multimedia appliances,

[0015] FIGS. 3 to 5 are practical examples of connection of processorsused for multimedia appliances to a bus,

[0016]FIG. 6 is a practical example of the structure of an elementarydata packet,

[0017]FIGS. 7 and 8 are practical examples of the structure of differentdata packets.

[0018]FIG. 9 shows the effect of time errors on data packets.

[0019] FIGS. 10 to 17 are practical examples of the structure ofdifferent data packets.

[0020]FIG. 18 is a practical example for the design of a configurationmemory and

[0021]FIG. 19 is a practical example of the design of a memory word forthe configuration memory according to FIG. 18.

[0022] In order to facilitate the understanding of the presentinvention, in the figures, only the components of those embodiments arerepresented, which are of importance in connection with the invention.The same components in the figures have the same reference symbols.

[0023] In general, for example, the following requirements can be set upfor a method and a system for the controlling and exchanging of data formultimedia appliances: Data rate: up to approximately 100 kbps Type ofdata: control and system data Topology: bus Transport medium: cablePacket-synch: edge-activated Medium termination: none Organization:peer-to-peer Type of linking: point-to-point, broadcast Arbitration:CSMA/CD Addressing: GUID, Node-ID Error protection: ARQ/CRC Management:register-based XON/XOFF Hot Plug & Play

[0024] It follows from the requirements given above that the individualappliances are linked through a cable, which runs from appliance toappliance. Thus the appliances must have two sockets. Appliances, whichare clearly end appliances (for example, camcorder), are exceptions tothis.

[0025] Appliances can be connected to the bus at any time and separatedfrom it (Hot Plug & Play). Information about the appliances and theirproperties are set up in a firmly agreed-upon structure under anagreed-upon base address.

[0026] The structure of the system will be explained below with the aidof the ISO/OSI layer model. This will show the locations where certainproperties were omitted in order to make realization at smallexpenditure possible.

[0027]FIG. 1 shows the layers of the present system. A physical layermakes transfer of individual data packets available. Since onlyindividual packet transactions are allowed in order to minimize the loadon the processor or microcontroller used in the individual appliances,the physical layer makes available services for the transfer of packetswith variable length.

[0028] A link layer provides mechanisms for access to the medium (mediumaccess layer: MAC layer), error protection as well as individual typesof packets. In addition, the link layer (device link control layer, DLC)ensures address handling. Each appliance contains a GUID (64 bit MACaddress), but this is not used for transfer since this would lead tounnecessarily high loading of the processors. For this reason, a NODE-ID(6 bit long) is allocated. The allocation of this NODE-ID is also thetask of the device link control layer (DLC).

[0029] In order to simplify the system, a network layer, as well as atransport layer, are omitted, as they are defined according to anISO/OSI layer model. They can be omitted because it is not intended tocombine various buses with different data traffic to one network.Therefore, routing mechanisms are not necessary.

[0030] A session layer can also be omitted which serves to furthersubdivide a communication, because, first of all, in the case of anerror, not the complete communication has to be repeated, and, secondlyto increase security (encoding of individual sessions). Since theplanned data blocks are small, the session layer is omitted. The contentof the individual data packets is defined in the presentation layer. Forthe present system, these are mainly the contents of the predefinedregister (CSR) as well as direct control commands (RC codes).

[0031] The individual appliances are defined in the application layer;since the individual appliances are not of importance in connection withunderstanding the present invention, description of the applicationlayer is omitted.

[0032] In order to avoid expenditure, two criteria must be observed withhighest priority for the realization of the physical layer, namely, assmall as possible additional hardware costs, for example, by using asimple bus coupler and components which are present in the appliances tobe linked anyway, for example, UART (universal asynchronous receivertransmitter). Individual partial regions of the physical layer will bedescribed in the following sections.

[0033] A possible bus topology is shown in FIG. 2. The bit transfertakes place with a standard UTP cable of category 3 (a pair of twistedwires) with a characteristic impedance of 100 Ω. For reasons of cost,standard chinch sockets are used for sockets. In order to avoidconfusion with Sat-Link, Audio or S-VHS sockets, other sockets can alsobe used (for example, jacks). However, the chinch socket represents themost cost-effective variant.

[0034] The bus is operated without termination OA. The linking of thebus is done by looping through appliances with two sockets, for example,video recorder VCR, DVD appliances DVD, TV appliances TV and satellitereceiver Sat. Only dedicated end appliances, for example, camcorder C,represent an exception and these are equipped with only one socket. As aresult of this, stubs are avoided.

[0035] As mentioned above, cost-effective realization between individualend appliances is possible only if existing resources can be utilized.Therefore, the protocol to be used is designed in such a way that anexisting UART can be used, in order to reduce the software load on theprocessor in the appliances.

[0036] With a predetermined base speed of the protocol, for example,115,200 bps or the clock frequency of the bus resulting from it and apredetermined maximum packet length, for example, 69 bytes, puresoftware evaluation is possible, since the processor requires only ashort time (6 ms) for receiving the packet, because receipt of thepacket must be done in real-time operation. Appliances or theirprocessors, for which this time is too long, can be signaled theirmaximum permissible packet length through a SPLIT_TIME-OUT register,which will be described later. The following decoding processes can bedone within the normal task- switching of the processor.

[0037] Problems in the utilization of existing UARTs could occur undercircumstances when the chosen clock frequency of the bus should be adivisor of the processor clocks of the appliances. As a result of this,it is impossible to adjust the frequency divider in such a way that theclock frequency of the bus (115,200 bps) be reached with the requiredaccuracy. Then, in order to use the UART, adaptation of the processorclock is necessary, but the effects of this on other processes must beverified accurately.

[0038] Several solutions are possible for producing an interface betweenappliance and bus.

[0039] In a first solution, it is planned to realize the interface as acomplete software solution. The access to the bus uses an input port andan output port of the processor in the appliance. This solution issuitable especially for all processors, which do not have an internalUART. For example, a edge-activated interrupt input is necessary forrecognition of start bits. After a start bit interrupt had occurred, theprocessor must remain in a read routine until the entire data frame(=packet) is read in. In order not to load the processor unnecessarily,there is a possibility of masking the used interrupt input with anexternal wiring for the rest of the data frame. Such a wiring will beexplained later.

[0040] A second possibility is suitable for processors ormicrocontrollers, which have an internal serial interface (UARTinterface) available. An output (TRX) is connected to the bus through anopen collector and an input (RXD) is utilized correspondingly. Maskingof the interface interrupt can be achieved here, too, through anexternal wiring. The software load of the processor is significantlylower in comparison to a solution without serial interface.

[0041] There are limitations with regard to the adjustable baud ratesfor the integrated UART module, as already indicated above. The baudrate clock is derived through an internal, adjustable hardware divisorof the CPU quartz crystal oscillator. Thus, the scanning of the possiblebaud rate values will be dependent on the microcontroller used. If thisdeviation obtained is outside the established tolerances of the bus datarate (in the Example, 115,200 bps), this still can be adjusted by avariation of the quartz clock. If this quartz clock change is notpossible for other reasons, then the serial interface can/must berealized through a software solution.

[0042] In the case of low-performance processors or microcontrollers,there is another possibility of using an external UART component inorder to take the load off the processor. In any case, such an externalcomponent represents a cost, which is not to be underestimated, as aresult of which change to a faster/more powerful microcontroller may bemore expedient.

[0043] In order to realize the bus, it is planned to make the busconnection through a twisted bus line (UTP) without termination, asindicated above. Spur lines should be avoided. The appliances make twoparallel-connected sockets available for transfer. Only end appliances,for example, camcorders, represent an exception. Activation is donethrough an open collector stage. As a result, 0 V is the dominant level(one appliance is sufficient to force the level on the bus) and isdefined as logically null. The open-collector stages are designed highimpedance (100 kΩ), in order to limit the current flowing through thebus, even in case of maximum bus occupancy.

[0044]FIGS. 3 and 4 show practical examples of open collector stages foractivation of the CPU processors used in the appliances. FIG. 3 shows apractical example without interrupt masking. FIG. 4 is a practicalexample with interrupt masking. FIG. 5 shows a practical example of anopen collector stage for the activation of a microcontroller CPU with aUART, in which interrupt masking is provided.

[0045] The time during which the interrupt is masked follows from a timeconstant T₁=R₁·C₁. The discharge time for C₁ through the dischargetransistor TR2 must be smaller than the transfer time for one bit. Thelatter will be referred to below as T_(e)=R₂·C₁.

[0046] When turning on transistor TR1, the base current through diode Dbetween base and collector is limited. This current goes to thecollector through the small on-voltage. During turning off, thetransistor TR1 requires much less time. A suitable diode D is, forexample, type BAT 85, a special switching diode.

[0047] The connection to the bus is done through socket B. In order toloop through the bus, a second bus can be connected parallel to the busB shown. The resistors of the open-collector stages have, for example,resistance values of R3=100 kΩ and R4=220 Ω.

[0048] In order to realize both a UART support as well as a puresoftware solution, the packets are designed in such a way that, at thebeginning of the packet, a UART can react as well as an interrupt can beactivated. Such a packet is shown in FIG. 6. The falling edge of a startbit ST triggers the read-in process of the packet. At the same time, theRC time unit (R₁, C₁) for interrupt masking is discharged through thenull bit and thus locks the following edges until the threshold valueafter transfer of a packet is reached again. Scanning the individualdata bits is now taken over by a software routine in processors withoutUART, or it is taken over by the integrated UART module of themicrocontroller. For example, the entire byte frame consists of tenbits, the start bit ST, eight data bits D0 to D7 and a stop bit. Forexample, the data bit D0 is set up as the bit with the lowest value inorder to achieve the desired compatibility with the UART. Yet, whentransferring several bytes, the highest value byte is transferred first.

[0049] As already stated above, up to 69 physical byte frames form oneframe of the physical layer. The byte frames are transferred directlyone after the other. Gaps occur only between the frames (arbitrationgap) and between the frame and acknowledge (acknowledge gap).

[0050] Each received frame is acknowledged by the addressed appliance(node) with an acknowledge signal. For example, the distance to theprevious frame should be 3±1 bit. Then there must be a gap of at least20 bit≅175 μs observed until a new message can be sent from an arbitraryappliance in the network. During this time, the time function element C₁(FIGS. 4 and 5) had to be charged to the operating voltage so thatinterrupt release occurs.

[0051] The link layer provides the appliance addressing, errorprotection as well as bus arbitration. Fair arbitration, that is, thesame arbitration probability and arbitration time for all appliances isachieved through a simple, random time-constant after the completion ofthe arbitration gap. In combination with CRC (error protection) andacknowledge, in this way reliable packet transfer is achieved withacceptable throughput.

[0052] Three different packets are provided for the bus. An ALIVE packetmakes it possible to realize the Hot Plug & Play without additionalhardware measures. One DATA packet makes labeled transfer of datapossible. A special case is the transfer of remote control commands.Finally, one CSR packet makes exchange of information between appliancespossible, for example, the abilities of the appliances or the innerstatus of the appliances. The CSR packet also makes register availablefor transactions (READ, WRITE, LOCK).

[0053]FIG. 7 shows the structure of a general header. The general headerconsists of two bytes, byte_0 and byte_1.

[0054] The first byte, byte_0, determines both the packet type tt, aswell as a target address dddddd. This facilitates rapid filtering of thepackets and leads to taking load off the processors in the appliances.For example, ALIVE packets are labeled as type 01, that is, the firsttwo bits of byte_0 have a coding which is logically zero and one. Forexample, if, in order to determine the network topology, all connectedappliances determined, all ALIVE packets can be evaluated very rapidly,while other packets are discarded. The target address is coded with thesix dddddd bit. If the lower half of the addresses is allowed forcoding, that is, the lower five bits, a maximum of 32 appliances can beaddressed plus the 3Fh (hexadecimal data) as broadcast address, which isprescribed for ALIVE packets. The upper half of the addresses can beprovided, for example, for future uses and services, such as point tomultipoint.

[0055] The second byte, byte_1, contains a modifier mm, whichcharacterizes either the service or the transaction type, and a sourceaddress ssssss, that is, the address of the sending appliance. ALIVE,data and RC code (remote control commands) are predefined as services.Another type is available for future use. In addition, a generic type isavailable, which can, for example, refer to the next byte fordescription of other services. READ, WRITE and LOCK are available astransactions and these will be described below.

[0056] A possible coding for the general headers is given below.

[0057] byte_0

[0058] 2 bit type: tt

[0059] 00=DATA

[0060] 01=ALIVE

[0061] 10=CSR request

[0062] 11=CSR response

[0063] 6 bit target address: dddddd

[0064] 00h-1Fh=target address of the appliance (NODE-ID)

[0065] 3Fh=broadcast, prescribed in case of ALIVE packets

[0066] byte_1

[0067] 2 bit modifier: mm

[0068] In the case of type=ALIVE

[0069] 00=valid

[0070] 01=invalidate

[0071] 10=reserved for future use

[0072] 11=reserved for future use

[0073] In the case of type=DATA

[0074] 00=ALIVE packet or RAW DATA

[0075] 01=RC code

[0076] 10=reserved for future use

[0077] 11=GENERIC DATA

[0078] In the case of type=CSR request/CSR response

[0079] 00=READ

[0080] 01=WRITE

[0081] 10=LOCK (test and modify)

[0082] 11=GENERIC TRANSACTION

[0083] 6 bit source address: ssssss

[0084] For error protection, for example, a 16 bit CRC code is used. Thecode is set up through the entire packet, but without start- and stopbits. As CRC code, for example, the code defined by ITU-T (for example,for HDLC) with the following data is chosen:

Generator polynomial: p(x)=x ¹⁶ +x ¹² +x ⁵ +x ⁰

Coding by: crc(x)=data(x)·x ¹⁶ mod p(X)

[0085] Initialization is not necessary, because a valid data word isalways given through the header with at least 2 bytes. The receiver cannow check either

data (X)·x ¹⁶ mod p(x)=crc(x)

or

(data(x)·x ¹⁶+crc(x))mod p(x)=0

[0086] for validity. It should be noted that the arithmetic is carriedout through the GF(2) (Galois field: binary range of numbers), that is,addition and subtraction of the coefficients take place without transfer(EXOR).

[0087] With the given CRC code, typical errors can be recognized inline-bound networks, that is, individual bit and double bit errors canbe recognized by scanning errors or threshold value errors (noise, phaseshift), and burst errors (EMV disturbances, for example, by electricmotors) can also be recognized.

[0088] The packets of the link layer are confirmed by an acknowledgepacket. The acknowledge packet follows the message directly, where thesignal gap (acknowledge gap) can be 3±1 bit. The acknowledge packet isdesigned in such a way that both in the case of point-to-point linkingas well as in the case of broadcast message a link layer acknowledge ispossible. The exact definition of the acknowledge and the evaluation inthe case of broadcast message will be described below.

[0089]FIG. 8 shows a possible practical example for an ALIVE packet. TheALIVE packet consists of four bytes, byte_0 to byte_n−1. Byte_0 andbyte_1 correspond to the general headed described above. The duration ofan ALIVE packet is accordingly 350 μs. Thus, the sending of one ALIVEpacket per second for each appliance represents a good possibility ofrealization, T_(AM)=1 s.

[0090] Thus, the bus occupancy with the assumption of 90 bit per ALIVEpacket (40 bit packet+4 bit acknowledge gap+10 bit acknowledge+36 bitarbitration gap) is usually below 1% in the normal case. Σ appliancesbus occupancy 2 0.16% 4 0.31% 8 0.62% 16  1.25% (32)  2.50%

[0091] Since the ALIVE packets are broadcast packets, that is, the ALIVEpackets are directed to all appliances connected to the bus, a specialacknowledge is agreed upon: the acknowledge is examined in order to fineout if at least one appliance has received the ALIVE packet correctly.Due to the dominance of the logical null, the following agreement ismade:

[0092] ACK_OK=0Fh

[0093] ACK_ERR=FFh

[0094] If the acknowledges occur at different times, start bits could beinterpreted as a logical null. However, it can be seen from FIG. 9 thatalways at least two bits remain in order to recognize that at least oneappliance was able to decode the ALIVE packet correctly. In FIG. 9,three acknowledges are shown for this, with 0 bit, −1 bit and +1 bittime error. The packet result obtained shows the two remaining bits.

[0095] The modifier mm in byte_1 of the ALIVE packet is needed forcollecting, in the case of linking two buses, the doubly presentNODE-IDs, which occurs in this case under certain circumstances. In thiscase, it is shown that the NODE-ID is invalid and must be negotiatedagain. The procedure necessary for this will be described later.

[0096]FIG. 10 shows a possible practical example for a DATA packet. TheDATA packets have the same general header with the type-labeling DATA.The total header is 3 bytes long, byte_0 to byte_2. The additional byte,byte_2, is coded as follows: Byte_2 ss: 2 bit transaction code (given bythe sender) 111111: 6 bit useful data length (number of bytes withoutheader and CRC)

[0097] This additional header byte makes coding as well as the usefuldata length 111111 possible, to adjust the receiving processor and theCRC decoder, as well as the coding of new attempts. This may becomenecessary when a packet is correctly received, but the answer is notsent or was perturbed during transfer. In this case, for example, thecontrolled appliance may already have switched a program so that whenthe controlling appliance makes a new attempt, this could lead to arepeated unintended program change. This case can be avoided by thetransaction code ss. The other bytes shown contain useful data.

[0098]FIG. 11 shows a possible practical example for a CSR packet. CSRpackets represent a special case of data packets and correspondinglyalso have a 3 byte long header, byte_0 to byte_2. The CSR packets canalready be recognized at the first bit, which is set to logic one. Thesecond bit t shows if we are dealing with a request or a response. Themodifier mm shows which transaction will be requested or answered. Thespecial characteristic consists in the next two bytes:

[0099] Byte_3 8 bit address (higher value byte of the 16 bit CSRaddress)

[0100] Byte_4 8 bit address (lower value byte of the 16 bit CSR address)

[0101] With the 16 bit CSR address, 64 kbytes can be addressed. The 64kbytes make all appliance-specific properties, as well as the memorylocations available for reading and writing of values. This structuremakes rapid inquiry of the system properties as well as simplehierarchical storage of all information in the network possible. Thearchitecture and memory occupancy of the implemented CSR architecturewill be described later. The address range prescribed for all appliancesis limited to 2 kbytes. The other represented bytes contain useful data.

[0102] The medium access layer must make available a fair access to theindividual appliances with optimized throughput at the same time. Sincethe bus should not require any additional hardware for the physicallayer and link layer, the access mechanism must be highly simplified.For example, a CSMA/CD mechanism (Carrier Sense Multiple AccessCollision Detection) can be used for this purpose.

[0103] As described above, the physical frame has two so-called gaps(signal gaps) which determine the system behavior, namely theacknowledge GAP and the arbitration GAP. These signal gaps control theaccess to the medium (bus). The individual appliances detect incomingpackets by the falling edge of the start bit after a set number of logicones. After release of the interrupt, either at the beginning of a newpacket or for sending, which occurs after about 20 bit timings, anappliance ready to send must wait for a random number of bit timingsbefore the sending process begins. Then, just before sending, it ischecked one more time if the channel is still free.

[0104] The random number of bit timings to be waited for is not chosenanew for each sending process in order to simplify the system, becausethis would necessitate an additional random number generator. Rather, itis provided that the NODE-ID, which, as described above, is allocatedrandomly, directly follows the additional time interval. Thus, themaximum gap between two packets is

20+32=52 bit (for the case, that a maximum of 32 appliances areallowed), from which a gap of 20+16=36 bit follows on the average.

[0105] The task of the device control layer is to allocate the NODE-ID.Each appliance is established by a 64 bit GUID, which can be constructedas follows: Byte 0-2: 3 byte vendor-ID 0x00D0D5h = vendor-ID of theApplicant Byte 3-7: 5 byte device ID) 0xAAAAXXXXXXh = vendor-ID of theApplicant AAAAh: not equal to 0xFFFEh and 0xFFFFh XXXXXXh: arbitrary

[0106] When allocating the device-ID, care must be taken that itcorresponds to the general scheme in the allocation of applianceaddresses of the particular manufacturer. The MAC address, which isunique for each appliance, is not suitable for use in the physical layerof the bus, since the number of addressable appliances and the length ofthe addresses is much too large. Therefore, within the bus, the NODE-IDis allocated, which is only 6 bit long, as described above in connectionwith the packet headers.

[0107] In order to ensure the randomness of the arbitration gap and tofurther reduce collision, the NODE-ID is allocated randomly. Here, therandomness is not strictly specified and therefore does not have to beproduced by a random number generator. Rather, random register contentsor simply the lower 6 bit of the MAC address are sufficient as aninitial value.

[0108] Before the NODE-ID selected in this way can be utilized, theappliance must wait for a duration of

[0109] N·T_(AM) with N=3 and T_(AM)=ALIVE packet interval.

[0110] As a result of this, it is ensured that ALIVE packets werereceived by all appliances and therefore all already allocated NODE-IDsare known. If the NODE-ID selected by the appliance is already present,another must be attempted, for example, by addition of the prime number17 (addition mode 32). The first NODE-ID, to be used without collision,is selected and is made known in the network with corresponding ALIVEpackets.

[0111] With this mechanism, the allocation of the NODE-IDs to thetask-related goal of Hot Plug & Play can be achieved without any greatexpenditure. An appliance reports itself by its ALIVE packets in thenetwork and therefore can be reached by all communication partners. Dueto the CSR architecture, which will be described below, now allappliances know what information is to be found and where. If anappliance is removed from the bus or is turned off, no additional ALIVEpackets are recognized any longer. An appliance is considered to besigned off when, after a time duration of

[0112] M·T_(AM) with M=2,

[0113] intervals, no ALIVE packet could be received anymore. Aftersigning off, an appliance must sign on again as described above, but anattempt should be made to use the latest valid NODE-ID again. Thisensures that very short and perhaps unintended signing off/signing onprocesses do not represent a load for all appliances, but are invisiblefor the appliances which are not participating in the communication. Inorder to make this possible, the particular NODE-ID used must be storedin a nonvolatile memory of the particular appliance, which is, forexample, assigned to the appliance processor, after it was establishedin the first sign-on process and was recognized as valid. However,generally, during turning off or signing off, the appliances can beturned off completely, that is, the appliance can be separatedcompletely from the network voltage. This is possible, because until theappliance is turned on again, this is considered not to be in thenetwork any longer, since it is recognized only through its ALIVE packetand because, after the appliance is turned on again, the appliance canobtain information very quickly about the present status of the networkby evaluating the ALIVE packets of the other active appliances. This canbe done quickly, since the ALIVE packets are sent approximately once persecond by each active appliance, as described above.

[0114] The individual appliances can check the status of the networkregularly or only if a transaction is intended, depending on theirperformance potential.

[0115] The procedure for allocating NODE-IDs described above functionswithin a bus. When two buses are combined (TV appliance and videorecorder with analog and digital satellite receiver), it may occur thatduplicate NODE-IDs appear although the individual NODE-IDs wereallocated correctly. If, in the evaluation of packets, any packetappears which contains its own NODE-ID as source address, this NODE-IDwill be allocated twice. In this case, in the appliances+ own ALIVEpacket, modifier mm, as described above, is set to INVALIDATE and bothappliances sign on again at the network, according to the describedmechanisms.

[0116] For example, the CSR architecture can be set up according to thestandard IEEE 1212 called “Control and Status Registers (CSR)Architecture for Microcomputer Busses”. The CSR architecture defines howthe appliances that are connected to a bus or to a network can be madeto react. The CSR architecture assumes that the appliances have aregister, the content of which can be read through the network with aread command and the value of which can be changed through a writecommand. The CSR architecture defines a generally 64 bit address spaceand an at least 2 kbyte register address space. This is subdivided intoa core-register region (0 to 511 byte), a bus-dependent register region(512 to 1023 byte) and a Read Only Memory (ROM) region (1024 to 2048byte). The CSR address space is virtual and can be imaged on the addressspace of the microcontrollers or processors in the appliances. However,an arbitrary imaging is permissible and frequently sensible since mostlyonly a few of the possible registers are implemented.

[0117] Reading access to the register (and the ROM) is done through theREAD transaction. The register contents can be modified with the WRITEand LOCK transactions. A transaction always consists of two messages, aCSR request and a CSR response.

[0118] Each appliance in the network can access the register of allother appliances with the aid of READ/WRITE/LOCK transactions. For thispurpose, the requester sends a CSR request to the target appliance. Therequest message contains among others the register address, the numberof bytes to be read or to be altered and, in the case of the writingrequest, the data. The target appliance answers with a corresponding CSRresponse, which contains the success status of the transaction, thetransferred bytes and in the case of a reading request, the data.

[0119] The standard IEEE212 defines the register fundamentally with a 32bit word size. Independently of this, write and read accesses caninvolve an arbitrary number of bytes. In the present practical example,it is provided that registers with an 8 bit word size are alsopermissible.

[0120] A high degree of error tolerance can be achieved by the fact thatthe CSR request and response are confirmed through the CRC andacknowledge of the link layer. In addition, a timeout transaction isdefined within which the response must be sent. Otherwise, thetransaction with the same transaction answer code can be repeated. Forexample, a transaction timeout of 500 ms is provided but this value canbe adjusted through the so-called SPLIT_TIMEOUT register.

[0121] The WRITE transaction consists of the WRITE request and thecorresponding WRITE response. A possible embodiment of the WRITE requestis shown in FIG. 12. The address is followed by two bytes less thangiven in byte_2, since the length given in 111111 contains the addressregister, bytes_3 and byte_4. The transaction answer code tt can beselected arbitrarily by the sender and serves to make assignments to theresponse possible.

[0122] The target appliance must send a response with the sametransaction answer code tt to the requester. The response code fieldrrrr in byte_3 signals the reason for success or failure. A possibleembodiment of the WRITE response is shown in FIG. 13. The response codefield rrrr can have, for example, the following meaning:

[0123] rrrr: 0000 Request processed successfully

[0124] 0100 Resource conflict, request can be repeated

[0125] 0101 Hardware error, data not available

[0126] 0110 No access (for example, ROM register)

[0127] 0111 Access to nonexisting register

[0128] The READ transaction consists of the READ request and thecorresponding READ response. The possible embodiment of the READ requestis shown in FIG. 14. The transaction answer code tt can be selectedarbitrarily by the sender and serves to make assignment to the responsepossible. The length 111111 given in byte_2 refers to the length of therequest packet. The number of bytes to be read is in byte_5 Byte_3 andbyte_4 contain the address register.

[0129] A possible embodiment of the READ response is shown in FIG. 15.The target appliance must send to the requester a response with the sametransaction answer code tt. The response code field rrrr in byte_3signals the cause of success or failure. The data follow after byte_4.The number of bytes is one less than the value in byte_2, since thisincludes the response code field, byte_3. The number of bytestransferred in the response message may be smaller than given in therequest, but it can never be larger. The meaning of the response coderrrr corresponds to the meaning given above for the response code rrrrin connection with the WRITE transaction.

[0130] The LOCK transaction represents a so-called READ/MODIFY/WRITEtransaction, and this can have many different embodiments. TheCOMPARE/SWAP transaction has a special meaning; this transaction has twoinput operands, the comparison data and the set data, as well as aresult value. It first of all compares the comparison data sent in therequest with the actual register content. If these are the same, theregisters are described with the set data and if they are different, theregister contents remain unchanged. The returned value is the oldregister value in each case.

[0131] The LOCK command allows several appliances to allocate resourcesof an individual appliance uniquely. This is achieved by, first of all,reading the old register value with a READ transaction and then, whensetting the register with the LOCK transaction to the desired new value,using the previously read value as comparison value. The LOCKtransaction will be successful only when the register content betweenthe READ and LOCK command has not been modified by a third appliance.

[0132] In contrast to IEEE 1212, which permits the LOCK transaction onthe 32 bit and 64 bit register, it is provided to define the LOCKtransaction for 8 bit and 32 bit word size. The LOCK transactionconsists of the LOCK request and the corresponding LOCK response. Apossible embodiment of the LOCK request is shown in FIG. 16. Thetransaction answer code tt can be selected by the sender arbitrarily andit serves to make assignment to the response possible. It should benoted that the length 111111 given in byte_2 contains the address aswell as the number of bytes for comparison and the set data. The twomust always be equally long.

[0133] A possible embodiment of the LOCK response is shown in FIG. 17.The target appliance must send a response with the same transactionanswer code tt to the requesting appliance. The response code field rrrrin byte_3 signals the cause of success or failure, as described above.After byte_4, as many byte data follow as given in the length data111111 in byte_2. The structure of the LOCK request corresponds to thatof the WRITE request and the LOCK response packet corresponds to that ofthe READ response.

[0134] The CSR registers are used to manage the network, theconfiguration of the appliances and the activation of the functionunits. The CSR address range is divided into several regions for thispurpose: 0000h-01FFh CSR core Standard register for bus control0200h-03FFh bus Bus specific register 0400h-07FFh CSR-ROM CSRconfiguration 0B00h-FFFFh FCP function control

[0135] The first two regions up to the address 03FFh serve for networkmanagement and will be described below. The structure and thepossibilities of the CSR-ROM region will also be described below. Inorder to show how extensions of the register range can be carried out,let us mention the memory division of the register range for theFunction Control Protocol (FCP) according to IEC 61883, which is used asan example above. For example, the protocol AV/C-CTS (AudioVideo/Control—Command and Transaction Set) is carried out by throughFCP, which contains protocols for activating all current electronicsentertainment appliances.

[0136] The CSR core and the bus-specific register essentially serve forthe management of the network. In the assigned address space, a fewregisters are prescribed:  0 STATE_CLEAR state and control information 4 STATE_SET sets STATE_SET bits  8 NODE_IDS required 12 RESET_STARTrequired (command_reset) 24 SPLIT_TIMEOUT_HI split requester timeout(seconds) 28 SPLIT_TIMEOUT_LO as above (fraction of seconds) 36 ARGUMENTdiagnostic r/w test interface 128-188 MESSAGE_REQUEST target address formessages 192-252 MESSAGE_RESPONSE as above

[0137] The two registers STATE_CLEAR and STATE_SET serve both as statusdisplay as well as for controlling the operational status of networknode. They define the following among others:

[0138] STATE=appliance is on online (1) or is still in theinitialization phase

[0139] OFF=appliance is on standby

[0140] The register NODE_IDS serves essentially to manage severalnetworked networks and buses, since, in addition to the NODE-ID, it alsodefines the network-ID. The register RESET _START permits newinitialization of the network node.

[0141] Split transaction are transactions which consist of request andresponse messages, separated in time, as is always the case for thetransactions described above. The advantage for the target appliance isthat the time requirements for processing a request can be adapted tothe processing performance of the appliance. With the SPLIT_TIMEOUTregisters, the appliance shows what the maximum length of time is neededfor processing a request, and therefore a requesting appliance knows howlong it must wait for the response. As second function, through theSPLIT_TIMEOUT register, the time-out can be changed from the outside,which, however, always requires cooperation of the target appliance.

[0142] The registers ARGUMENT and MESSAGE are optional, and theirfunction is not specified uniquely beforehand.

[0143] For the proposed bus, it is expedient to define additionalregisters, for example, registers which establish uniquely what type ofconnection is used: PlugRegister for chinch plug connection PlugRegisterfor SCART plug connection

[0144] The task of the ROM configuration is the description of theappliances with regard to their static properties. These include, on theone hand, the Globally Unique ID (GUID), with which each appliance canbe identified uniquely, and, on the other hand, a description of theproperties of the appliances. The two types of information together areneeded to make the attempted Hot Plug & Play possible.

[0145] The ROM configuration consists of a number of 32 bit inputs,which are also called quadlets. The ROM region is divided into twopartial regions, the Bus Info Block and the Root Directory, as it isshown, for example, in FIG. 18. The Root Directory usually containsadditional registers with system-describing information.

[0146] The first word W1 of the Bus Info Block contains the followingparameters: Info length length of the Bus Info Block measured inquadlets CRC length number of quadlets, which are protected by the nextCRC CRC 16 bit CRC (as described above)

[0147] The second word W2 contains the name of the bus standard, codedin ASCII characters, for example, GRL1. The third word W3 isbus-specific and can be defined according to need. There must be atleast one max_rec field present, which determines the maximumpermissible length of messages. The max_rec field can be contained inthe second byte of the quadlet W3. The fourth and fifth word W4 and W5contain the globally unique ID, consisting of the 24 bit manufacturercode, followed by a 40 bit appliance number.

[0148] The structure of the Root Directory, as well as the structure ofall other directories, can be constructed as proposed in IEEE 1212. Eachdirectory begins with a 32 bit directory header W6. This consists of two16 bit inputs, of which the first one (root length) gives the number offollowing quadlets with directory information and the second one (rootCRC) contains the CRC on the directory.

[0149] Each directory input Wn is 32 bit long and is divided into twobits for type, six bits for key and 24 bits for value, as shown in FIG.20. Data, which is less than 24 bit, is deposited directly into the 24bits of the field value. The type is set to 00 in this case. Longerdata, for example, text, are addressed indirectly. In these cases, thefield value contains an offset in quadlets to the actual data. The typeis set in this case to 01. The types LEAF, type set to 10, andDIRECTORY, type set to 11, permit a structure deposition of informationby forming subregisters. In the case of LEAF, the field value containsan offset to a Leaf Directory, and in the case of DIRECTORY, the fieldvalue contains an offset to a directory.

[0150] While a large number of the codings possible for the 6-bit longfield key is fixed (IEEE 1212), eight keys can be defined freely.

[0151] The present invention was described so far in combination withmultimedia appliances, electronics entertainment appliances. However, itis obvious that other appliances can also be operated in the busdescribed, in case they have a suitable microcontroller or processor,which can be used for the evaluation of data packets described above.

1. Method for controlling and/or for exchange of data for multimediaappliances, especially for electronics entertainment appliances, inwhich the individual appliances are connected with the aid of a bus,characterized by the fact that each activated appliance sends a messagethrough the bus to the other activated appliances within a predeterminedtime period, the other activated appliances can recognize with the aidof messages if the particular appliance is activated, the otherappliances can no longer recognize the particular appliance as beingactive when no message was received at least after the lapse of apredetermined time period, and an appliance, which is activated for thefirst time or repeatedly, sends messages through the bus to the otheractivated appliances only after a time period which is longer than orequal to the predetermined time period.
 2. Method according to claim 1,characterized by the fact that the messages of each activated appliancehave a component which describes the properties of the appliance. 3.Method according to claim 1 or 2, characterized by the fact that eachactivated appliance sends a unique identification [NODE-ID] and that theunique identification (NODE-ID) is a component of the messages of theappliance.
 4. Method according to claim 3, characterized by the factthat the unique identification (NODE-ID) is established randomly. 5.Method according to claim 3, characterized by the fact that the uniqueidentification (NODE-ID) is derived from a superior uniqueidentification (GUIDE) where the superior unique identification (GUIDE)contains more information than the unique identification (NODE-ID). 6.Method according to one of claims 3 to 5, characterized by the fact thateach appliance, which is activated for the first time or repeatedly,establishes its unique identification (NODE-ID) only after a time periodwhich is longer than or equal to the predetermined time period, where,during the time period the messages of the other active appliances areevaluated in order to determine the unique identifications (NODE-ID)contained in them, in order to establish its unique identification(NODE-ID) not equal to the established unique identifications (NODE-ID)of the other active appliances.
 7. Method according to one of claims 1to 6, characterized by the fact that the active appliances evaluate themessages of other active appliances continuously.
 8. Method according toone of claims 1 to 6, characterized by the fact that the activeappliances evaluate the messages of the other active appliances onlybefore they control these and/or before they exchange data with these.9. System for the control and/or for the exchange of data for multimediaappliances, especially electronics entertainment appliances, in whichthe individual appliances are connected with the aid of a bus,characterized by the fact that each appliance has a bus interface and aprocessor, through which it sends messages through the bus to the otherappliances within a predetermined time period, the other appliancesreceive the sent messages with their bus interfaces and evaluate themwith the processors, where the evaluation of the messages shows whichappliances are activated, where appliances are recognized as not beingactive, when, after the elapse of a certain time which corresponds atleast to the predetermined time period, no message was received from theparticular appliance, and an appliance which was activated for the firsttime or repeatedly sends its own messages with the aid of the businterface through the bus only after a time period which is longer thanor equal to the predetermined time period.
 10. System according to claim9, characterized by the fact that the messages of each activatedappliance have a component which describes the properties of theappliance, where the properties are stored in a memory of the particularappliance.
 11. System according to claim 9 or 10, characterized by thefact that each activated appliance has a unique identification (NODE-ID)and that the unique identification (NODE-ID) is a component of themessages of the appliance, where the unique identification (NODE-ID) isstored in a memory of the particular appliance.
 12. System according toclaim 11, characterized by the fact that the unique identification(NODE-ID) is established with the aid of a random generator.
 13. Methodaccording to claim 11, characterized by the fact that a uniqueidentification (NODE-ID) is derived by the processor from a superiorunique identification (GUIDE), where the superior unique identification(GUIDE) is stored in memory of the appliance and contains moreinformation than the unique identification (NODE-ID).
 14. Methodaccording to one of claims 11 to 13, characterized by the fact that eachappliance, which is activated for the first time or repeatedly,establishes its unique identification (NODE-ID) with the aid of itsprocessor only after a time period which is longer than or equal to thepredetermined time period, where, during the time period, the messagesof the other active appliances are evaluated to establish the uniqueidentifications (NODE-ID) contained in them in order to make the uniqueidentification (NODE-ID) not equal to the established uniqueidentifications (NODE-ID) of the other active appliances.
 15. Methodaccording to claims 9 to 14, characterized by the fact that the activeappliances evaluate the messages of the other active appliancescontinuously with the aid of their processors.
 16. Method according toone of claims 9 to 14, characterized by the fact that the activeappliances evaluate the messages of the other active appliances withtheir processors only before other appliances are controlled and/orbefore data are exchanged with other appliances.
 17. Multimediaappliance for controlling and/or exchanging data with other multimediaappliances, especially electronics entertainment appliances, with a businterface and a processor, characterized by the fact that in theactivated state, the appliance sends messages within a predeterminedtime period with the aid of the processor through the bus interface, theappliance receives the incoming messages at the bus interface andevaluates it with the aid of the processor, where the evaluation of themessages gives the information if other appliances are activated, whereappliances are recognized as being not active when, after the elapse ofa time period which corresponds at least to the predetermined timeperiod, no message is received from the appliances, and the appliance,when it is activated for the first time or repeatedly, sends its ownmessages with the processor through the bus interface only after a timeperiod which is greater than or equal to the predetermined time period.